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High speed multi serial-link devices are rapidly applied in the field of network server and switch. To achieve high pin count (exceeding 2,000 pin) and high speed devices, we have been developing FC-BGA (Flip-chip BGA) package applied high-density organic substrate to achieve multi Gbps transmission [1]. The demand of signal speed approaches 28Gbps, and multi-lane serial links are also required. There...
In order to launch spin transfer torque-based magnetoresistive random access memory into mass production below the 40 nm technology node, high performance perpendicularly magnetized magnetic tunnel junctions (pMTJs) are crucial. One of the key issues for pMTJs is to ensure compatibility with conventional back-end-of-line (BEOL) heating process, where thermal tolerances over 350 for standalone...
Through Architecture-Algorithm co-design for Video Mining Applications we designed a scalable Manycore processor consists of clustered heterogeneous cores with stream processing capabilities, and zero-overhead inter-process communication through FIFO with a hardware-software mechanism. For achieving high-performance and low-power consumption, especially so as to reduce memory access required for Video...
We have developed a fabrication technology of fine-pitch cone shape Au bump array using nanoparticle deposition method for 3D LSI chip stacking. 1024-bit wide bus chip-to-chip interconnection circuit called Cool Interconnect has been also developed using fine-pitch bump joint array technology and precise flip chip bonding technology. Such a wide bus chip-to-chip interconnection is suitable instead...
3-D Multi-Chip stacking is a promising technology to overcome the “memory wall”, “power wall”, “ILP wall”, and “utilization wall”. However, a chip to be stacked should be low-power enough to avoid heat issue. On the other hand, such system can benefit from its scalability, flexibility, short time-to-market, especially wide and short latency chip interconnect drives changes on microprocessor architecture...
3D multi-chip stacking is a promising technology poised to help combat the “memory wall” and the “power wall” in future multi-core processors. However, as technology scales and the chip sizes increase due to the number of transistors, interconnects have become a major performance bottleneck and a major source of power consumption for microprocessors. In this article, we introduce a TSV-based ultra-wide...
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