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A new Lateral insulated-gate bipolar transistor (LIGBT) structure on SOI substrate, called controlled anode LIGBT (CA-LIGBT), is proposed. The design of the new structure results in high breakdown voltage and good trade off between turn-off time and on-state voltage drop. Simulation results show that the CA-LIGBT has about 85.0% reduction in turn-off time and about 20.0% increase in on-state voltage...
A new super junction LDMOS (SJ-LDMOS) on partial silicon-on-insulator (SOI) with composite substrate is presented in this paper. The thin super junction structure on the buried oxide (BOX) provides the surface low on-resistance path, which is attributed to the heavy doping trait of SJ. The N-buffer layer is introduced under the BOX to sustain vertical voltage, which reduces the substrate-assisted...
A novel NFFP HVI structure which implements high breakdown voltage without using additional FFP and process steps is proposed in this paper. An 850 V half bridge gate drive IC with the NFFP HVI structure is experimentally realized by using a thin epitaxial high voltage BCD process. Compared with the conventional MFFP HVI structure, the proposed NFFP HVI structure shows simpler process and lower cost...
A novel structure of 4H-SiC bipolar junction transistor (BJT) with floating buried layer (FBL) in the base epilayer is presented. Numerical simulations are performed to demonstrate that the current gain shows an approximately 100% increase due to the creation of buried layer electric-field. However, the variation rate of current gain is decreased sharply indicating FBL structure with high current...
REBULF (reduced bulk field) and ENDIF (enhanced dielectric layer field) technologies are used in the design of lateral power devices to improve breakdown voltage. The two technologies have been shown to offer good performance in a variety of application domains, both in bulk silicon and SOI substrates. This paper aims to offer a compendious and timely review of the two technologies and some works...
The formula of silicon critical electric field ES,C is given as a function of silicon film thickness ts from an effective ionization rate aeff which is experimentally obtained by taking threshold energy epsivT into accounting for electron multiplying. By the proposed ES,C, quantificational dependence of vertical breakdown voltage VB,V of SOI high voltage devices on top silicon thickness ts and dielectric...
In this paper, a novel substrate engineered power MOSFET with partial floating buried-layer is proposed. The proposed LDMOS with 2 mum thin epitaxial layer is designed . It is demonstrated that new electric field generated by the buried-layer modulates electric field in drift region and the voltage handling capability is enhanced. Influences of length, thickness and doping concentration of the buried-layer...
A new CMOS compatible super junction LDMSOT structure is designed with N+-floating layer embedded in the high-resistance substrate, which suppresses charges imbalance effect resulting from substrate-assisted depletion N-type pillar, and the high electric field around the drain is reduced by N+-floating layer which causes the redistribution of the bulk electric field in the drift region. The new structure...
A new CMOS compatible super junction LDMSOT structure is designed with N+-floating layer embedded in the high-resistance substrate, which suppresses charges imbalance effect resulting from substrate-assisted depletion N-type pillar, and the high electric field around the drain is reduced by N+-floating layer which causes the redistribution of the bulk electric field in the drift region. The new structure...
The two structures of over 650V MR & MR SLMFFP double RESURF LDMOSs with HVI are experimentally realized using SPSM BCD process for high side gate drive IC. The experimental results, coincident with the three-dimensional simulations, show that the breakdown voltage of LDMOS will increase by reducing the width of HVI metal line. The breakdown voltages of the MR double RESURF LDMOS are 670V, 760V,...
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