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An ultra-low Ron, sp SOI LDMOS with an improved BV is proposed and its breakdown mechanism is investigated. The device features a variable-k dielectric trench and a P-pillar beside the trench (VK-P). The P-pillar extending from the P-body to the trench bottom not only acts as the vertical junction termination extension (JTE), but also forms an enhanced vertical RESURF (reduced surface field) structure...
In this paper, a novel substrate engineered power MOSFET with partial floating buried-layer is proposed. The proposed LDMOS with 2 mum thin epitaxial layer is designed . It is demonstrated that new electric field generated by the buried-layer modulates electric field in drift region and the voltage handling capability is enhanced. Influences of length, thickness and doping concentration of the buried-layer...
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