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An ultra-low Ron, sp SOI LDMOS with an improved BV is proposed and its breakdown mechanism is investigated. The device features a variable-k dielectric trench and a P-pillar beside the trench (VK-P). The P-pillar extending from the P-body to the trench bottom not only acts as the vertical junction termination extension (JTE), but also forms an enhanced vertical RESURF (reduced surface field) structure...
A lateral power MOSFET with the extended trench gate is proposed in this letter. The polysilicon gate electrode is extended to the substrate, which improves the breakdown voltage (BV) and specific on-resistance (Ron). It indicates by simulation that the Ron of 1.86mΩ.cm2 with a BV of 174V in the proposed structure is nearly 53% less than the Ron of 3.96mΩ.cm2 with a BV of 126V in the typical structure.
A novel non-uniform multi-reversed-junction power MOSFET is presented in this paper. The high and uniform electric field in substrate is achieved due to modulating from space charges in the buried layers during operation in the blocking mode, and the breakdown voltage is improved considerably. A detailed study of the influence of various important parameters on blocking characteristics was carried...
A novel deep trench SOI LIGBT with enhanced safe operating area has been proposed. Deep trench gate electrode, reaching buried oxide layer, has been directly introduced for achieving low on-resistance. Heavily doped p+ region at the emitter side, which sandwiches between the n-drift region and n+ emitter region, is provided as holes bypassing path for ensuring enhanced forward biased safe operating...
Device simulations are applied to find out the effects of floating island thickness (dF) and doping concentration (Np+) in power floating island MOSFET (FLIMOS). The simulation results show that the specific on-resistance (Ronmiddotsp) increases by enlarging dF while Np+ produce little influence on Ronmiddotsp; When Np+ is low, the breakdown voltage (Vbr) improves by enlarging dF; When Np+ is high,...
In this paper, a novel substrate engineered power MOSFET with partial floating buried-layer is proposed. The proposed LDMOS with 2 mum thin epitaxial layer is designed . It is demonstrated that new electric field generated by the buried-layer modulates electric field in drift region and the voltage handling capability is enhanced. Influences of length, thickness and doping concentration of the buried-layer...
A novel 2-mum thin-drift-layer power MOSFET with an n-type floating buried layer (FBL) in substrate is proposed in this letter. Since the charges in the buried layer modulate the bulk electric field, a nearly uniform electric field is obtained, and the vertical breakdown voltage (BV) is significantly improved. Simulation results show that the BV of the proposed FBL lateral double-diffused MOSFET (LDMOSFET)...
A new CMOS compatible super junction LDMSOT structure is designed with N+-floating layer embedded in the high-resistance substrate, which suppresses charges imbalance effect resulting from substrate-assisted depletion N-type pillar, and the high electric field around the drain is reduced by N+-floating layer which causes the redistribution of the bulk electric field in the drift region. The new structure...
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