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This paper presents the design of a power- and area-efficient, high-performance dual-path receiver analog front-end (AFE) for wide multistandard applications of 8.5–11.5 Gb/s, such as 10GBASE-LRM, 10GBASE-KR, 10GBASE-CX1, and 10GBASE-LR/SR. A common programmable gain amplifier (PGA) with programmable peaking is followed by ADC-based and slicer-based paths. The ADC-based path employs a low-power, 6-bit...
The demand for bandwidth has fueled the deployment of 10 Gb/s traffic over legacy data links such as serial backplanes (10GBase-KR) and multimode fiber (10 GBase-MMF) which were originally intended for much lower data rates. Under severe channel impairments, a DSP-based transceiver provides robust performance and enables power/area scaling with processes. This work describes a 65 nm CMOS AFE integrated...
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