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A new circuit technique is proposed in this paper for reducing both the subthreshold and gate oxide leakage power in the domino logic circuits. Three high-Vt sleep transistors are added to the standard domino logic circuit to place the circuit into low leakage state. Proposed circuit is evaluated at 110°C and 25°C. At 110°C, proposed circuit reduces leakage power consumption by up to 63%, and at 25°C,...
A circuit technique is proposed in this paper for simultaneously reducing both subthreshold and gate-oxide leakage power consumption at high and low temperatures in footed domino logic circuits. A high Vt pMOS pull-up technique with feedback control utilizing both multiple-Vt and multiple Tox is added between the footer node and dynamic node to place footed domino logic circuit into a low leakage...
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