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To study dynamic evolution law of mechanical reliability caused by wear, gear transmission system is taken as a research object. Considering the effect of clearance caused by wear on gear teeth load in double meshing area, the formula of dynamic distribution load which is undertaken by two adjacent teeth is deduced. And the distributed pressure and meshing speed, which should be taken into account...
This paper focused on the delamination study of low profile leadframe package with exposed pad (eLQFP). In this type of package, a specification of silver plating area is required for bond pad. With the shrinkage of the non-plating pad area, and because of low adhesion strength between silver and mold compound, the interface of mold compound and die-pad in the silver plating area may potentially delaminate...
In this work we have demonstrated, for the first time, a 0.605μm2 dual core oxide (DCO) dual Vdd 8T SRAM cell in 45 LPG triple gate oxide CMOS process for use as L1 cache for high performance low leakage mobile applications. The DCO 8T SRAM operates under dual voltage supplies with write assist. Compared to traditional single-end 8T cell, DCO 8T SRAM showed the same performance with only half the...
As the progression of 45/40nm ELK devices into mainstream semiconductor assembly manufacturing process increases, the drive to achieve adoption without major changes to process and equipment infrastructure while meeting the superior yield necessary is high. The main goal of this article is to share learning's and provide solutions for integration of 45/40nm ELK devices into Flip Chip and Wire Bond...
Copper pillar bumping is a promising solution to cope with the challenges which flip chip packages face when bump pitch size keep shrinking. A large FCBGA (flip chip ball grid array) package for 45 nm Cu/Low-K device with Cu pillar bumps is chosen to investigate the package reliability. Finite element models have been built with multi-level sub-modeling technique to consider the detailed Cu/Low-K...
This paper will focus on the IEC 61850 process bus architecture design for a mesh corner transformer bay within National Grid. A range of architectures can be applied, depending on the requirements for each substation such as reliability, availability and cost. Different possible architectures for the bay are designed. The system reliability and availability figures are estimated for each architecture...
Flip chip packaging of ultra fine pitch integrated circuits (ICs) on organic substrates aggravates the stress-strain concerns, requiring a fundamentally different system approach to interconnections, underfill, interfaces, and the substrate. This work demonstrates a novel interconnection solution with excellent reliability for ultra-fine pitch (~30 mum) silicon (Si) on organic first level interconnections...
One promising application of CNTs in microelectronics is to use vertically aligned CNT (VACNT) arrays as novel thermal interface materials (TIMs). No doubt that the vertical alignment makes the best of the extremely high longitudinal thermal conductivity of individual CNTs; however, it is the CNT/substrate interface that exerts the main restriction on phonon transport through a TIM layer. There are...
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