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Gate first 0.59 nm EOT HfOx/metal gate stacks for 16 nm node application are demonstrated for the first time. By controlling O during HfOx deposition, ldquozerordquo low-k SiOx interface (ZIL) forms despite a 1020degC activation anneal. This 0.59 nm EOT is a 30% improvement over a state of the art 32 nm HK/MG technology. We compare and demonstrate for the first time the improved scalability of ZIL...
We have studied key parameters for controlling threshold voltage (Vth) variation and strain maintenance of gate first SiGe channel pMOSFETs. By overcoming 1) Ge diffusion and 2) strain relaxation during source/drain activation, we for the first time demonstrate high Ge% (50%) SiGe channel with millisecond flash anneal. Optimizing the thermal budget with millisecond anneal keeps the Vth variation same...
The use of millisecond annealing to meet ultra-shallow junction (USJ) requirements for sub-45 nm CMOS technologies is imperative. In this study, a detailed investigation of the effects of flash annealing on MOSFETs with Hf-based gate dielectric and metal gate electrodes is presented. The flash anneal process is found to be compatible with the high-κ/metal gate stack, in terms of gate dielectric reliability,...
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