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Timing-related defects are a major cause of test escapes and field returns for very deep-submicron (VDSM) integrated circuits. Small-delay variations induced by crosstalk, process variations, power supply noise, and resistive opens and shorts can cause timing failures in a design, leading to quality and reliability concerns. This article describes the authors' work with a previously proposed test-grading...
For sub-nanometer designs, testing for small-delay defects (SDDs) is essential to achieve low defect escapes for the manufactured silicon. Existing solutions for testing SDDs are not practical for high-volume production environments due to large pattern count or long compute time, or both. In this paper, we present a production-friendly method that takes the circuit topology into account while generating...
Testing for small-delay defects (SDDs) is necessary for ensuring product quality in smaller technology nodes. Current tools such as transition-delay fault (TDF) ATPGs and timing-aware ATPGs are either inefficient in detecting SDDs or suffering from large pattern count and CPU runtime. Furthermore, none of these methodologies take into account the impact of pattern-induced noises, e.g., power supply...
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