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We report on the promise of dual channel materials using FinFETs for high-performance CMOS for sub 22 nm technology node. We demonstrate pFinFETs with all SiGe channel formed by Germanium condensation onto a Silicon-On-Insulator carrier wafer (SiGeOI) followed by cMOS processing. The devices exhibit 3.6X hole mobility enhancement over Silicon (100) while allowing for VTH control with single high-k...
We have studied key parameters for controlling threshold voltage (Vth) variation and strain maintenance of gate first SiGe channel pMOSFETs. By overcoming 1) Ge diffusion and 2) strain relaxation during source/drain activation, we for the first time demonstrate high Ge% (50%) SiGe channel with millisecond flash anneal. Optimizing the thermal budget with millisecond anneal keeps the Vth variation same...
For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1 nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4 nm) SiOx interface layer. A secondary mechanism, Ge doping (ges4%) in high-k, possibly by up diffusion, also results in higher leakage. With...
We report on new observations of hot carrier (HC) degradation in strained Si/Si1-xGex(x = 0.2 to 0.5) p-MOSFETs. By using low voltage current-voltage measurement coupled with carrier separation, we are able, for the first time, to easily distinguish the energy distribution of the interface traps. High-K dielectrics on SiGe p-channel show higher interface traps generation located close to conduction...
High-performance sub-60 nm Si/SiGe (Ge:~75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high-kappa/metal gate stacks with ~1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length (Lg) devices demonstrate not only controlled short channel effects, but also an excellent on-off current (Ion/Ioff) ratio (~5times10...
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