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This paper presents a new model for understanding the saturated time dependence of hot-carrier degradation in LDD nMOSFETs. The peak of the lateral field, and thus the zone of high injection current, moves into the LDD region where generated interface states are of almost no influence on the MOSFET I(V)-characteristics.
In this paper various stages as appearing in digital logic, like inverters, NANDs, NORs, and transfer gates are hot-carrier stressed. Transient effects and the one of voltage combinations are discussed and an estimation for a realistic lifetime criterion is given.
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