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In this paper, we present an array of 160x128 pixels capable of detecting the ToA of single photons, implemented in 0.13μm CMOS technology. The sensor is partitioned into 4 identical quadrants that are served by a balanced clock tree so as to minimize skews and to ensure the fastest possible readout process. The pixels in the rows are read out in rolling shutter mode in two directions (top and bottom)...
A 3×3 prototype image sensor array consisting of 2μm diameter CMOS avalanche photodiodes with 3-transistor NMOS pixel circuitry is integrated in a 90nm CMOS image sensor technology. The 5μm pixel pitch is the smallest achieved to date and is obtained with <;1% crosstalk, 250Hz mean dark count rate (DCR) at 20C, 36% photon detection efficiency at 410nm (PDE) and 107ps FWHM jitter. The small pixel...
We report on the design and characterization of a 32 times 32 time-to-digital converter (TDC) array implemented in a 130 nm imaging CMOS technology. The 10-bit TDCs exhibit a timing resolution of 119 ps with a timing uniformity across the entire array of less than 2 LSBs. The differential- and integral non-linearity (DNL and INL) were measured at plusmn 0.4 and plusmn1.2 LSBs respectively. The TDC...
A Time-to-Amplitude Converter (TAC) with embedded analog-to-digital conversion is implemented in a 130-nm CMOS imaging technology. The proposed module is conceived for Single-Photon Avalanche Diode imagers and can operate both as a TAC or as an analog counter, thus allowing both time-correlated or time-uncorrelated imaging operation. A single-ramp, 8-bit ADC with two memory banks to allow high-speed,...
We report the design and characterisation of a 32times32 time to digital (TDC) converter plus single photon avalanche diode (SPAD) pixel array implemented in a 130 nm imaging process. Based on a gated ring oscillator approach, the 10 bit, 50 mum pitch TDC array exhibits a minimum time resolution of 50 ps, with accuracy of plusmn0.5 LSB DNL and 2.4 LSB INL. Process, voltage and temperature compensation...
A new integration based fluorescence lifetime imaging microscopy (FLIM) called IEM has been proposed to implement lifetime calculations. A real-time hardware implementation of this IEM FLIM algorithm suitable for a single photon avalanche diode (SPAD) array in 0.13 mum CMOS technology is now implemented on FPGA. A widefield microscope was adapted to accommodate the array and test it on biological...
The track-before-detect processing technique has been employed in numerous computer vision based algorithms to address the dim target detection problem. In this processing approach, target information (as often provided by an image processing stage that has emphasised target features or suppressed unwanted noise) is integrated over a period of time before the detection decision is made. In this paper,...
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