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The decades long development in shrinking footprint and improving performance of photonics integrated circuits has seemingly slowed down in recent years, posing problems in e g interconnects in data centers with their ever increasing power requirements. Thus, routes to a continued development towards smaller footprint, lower power, higher performance integrated nanophotonics will be presented and...
This paper explores the possibility to use insulating spin-on dielectric materials for 2.5D interposers. Up to 7 photosensitive materials have been investigated in terms of minimum line/space and via resolution to determine the maximum wiring density. In addition the electrical performances of the best materials were assessed in DC and RF to extract the dielectric constant and loss tangent. Finally...
A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various...
We have compared a number of well known plasmonic guides in terms of power confinement, normalized power density, and propagation loss. We have identified the relative advantages and limitations of these guides.
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