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A versatile recognition processor is presented that comprises 2.1M transistors using a 90 nm CMOS technology. It performs detection and recognition from image/video, sound and acceleration signals with energy consumption of sub-mJ/frame. The versatility and the power efficiency are attributed to optimal architecture design employing Haar-like Feature and Cascaded Classifier.
This paper presents a versatile recognition processor that performs detection and recognition of image, video, sound and acceleration signals, while dissipating 0.15 muW/fps to 0.47 mW/fps. Given the low power dissipation of sub-mW/fps, this processor is suitable for use in portable electronics and wireless sensor networks (WSN). For instance, it detects human faces from a QVGA image with 81% accuracy...
This article presents the multiobject parallel recognition architecture of a versatile recognition processor (VRP) that detects and recognizes objects from images, videos, sounds, and acceleration signals. It offers eight times better power efficiency than conventional object recognition processors, making it ideal for mobile application platforms and wireless sensor network systems.
A 0.79mm2 29mW real-time face detection core is fabricated in a 0.13mum CMOS technology. It consists of 75k gate logic, 58kbit SRAM, and the ARM AMBA bus interface. Comprehensive optimization in both algorithm and hardware design improves performance and reduces area and power dissipation. The core can detect 8 faces per frame at 30 fps. Face detection accuracy is 92%
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