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The paper describes a mixed-mode ASIC composed of a fast readout architecture that interfaces with a matrix of 4096 Monolithic Active Pixel Sensors (MAPS). The matrix has 128 columns and 32 rows of pixels and is divided into 256 regions of 4 times 4 pixels, named macro-pixels (MPs). The chip is an upgrade of a smaller version having 256 pixels that was designed and tested. The two chips were designed...
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