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A 512 kbit static random access memory has been designed and fabricated in a single-poly, six-metal 180 nm CMOS technology, with 1.8 V supply. The circuit has been designed to be radiation hard. The basic memory cell is a six transistor cell with a Miller capacitor between the internal latch nodes, to mitigate single event upset. Architectural and circuital solutions are also proposed to mitigate...
This paper proposes a design methodology for a digital library of cells resistant to cosmic radiation. Most important effects due to radiation are avoided or mitigated using ad hoc design techniques. Fault injection techniques are used to validate the design. Simulations results demonstrate that the cells designed in a 180 nm CMOS technology are tolerant to 1.5 mA current peak due to interaction with...
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