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This paper proposes a novel traffic engineering method using on-chip diorama network that consists of virtual nodes and virtual links. The diorama network is implemented on reconfigurable processor DAPDNA-2. In these years, traffic engineering has widely researched to guarantee QoS (quality of service). The proposal is an experimental solution with the on-chip diorama network, where virtual links...
Replica placement problem is to select a subset from a group of potential nodes to put replicas in Content Distribution Network (CDN). It is derived from the set cover problem which is known to be NP-hard. So it is difficult to calculate the large-scale replica placement problem on a program counter-based processor. Several greedy algorithms are proposed in order to decrease calculation time. However,...
This paper proposes fast parallel link-disjoint path algorithm using dynamically reconfigurable processor and implements it on DAPDNA-2 (IPFlex Inc) which is newly structured. The conventional k-shortest path algorithm finds multiple link-disjoint paths between the source node and the destination node. When the network scale is large, the calculation time of k-shortest path algorithm increases rapidly...
This paper proposes a parallel shortest path-searching algorithm and implements it on a newly structured parallel reconfigurable processor, DAPDNA-2 (IPFlex Inc). Routing determines the shortest paths from the source to the ultimate destination through intermediate nodes. In open shortest path first (OSPF), Dijkstra's shortest path algorithm, which is the conventional one, finds the shortest paths...
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