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We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by the deepest trenches, this architecture enables a full use of the back bias while staying compatible with both standard bulk design and conventional SOI substrates. We demonstrate in 20nm ground...
High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/µm and 1.25mA/µm, and Ieff of 0.95mA/µm and 0.70mA/µm at Ioff =100nA/µm and VDD of 1V, for NFET and PFET,...
Two implantation based schemes were explored for ETSOI NFET devices targeted for the 20nm node. Amorphization of the thin SOI is a key issue for the implant pre RSD scheme. This can be alleviated by implanting through liner. Variability is the key issue for the implant post RSD scheme which can be alleviated by good process controls and by the use of a two step epitaxy scheme.
FinFET devices achieving N/P Ion values of 1250/950 uA/um at 100nA/um at 1V, 1300/1000 uA/um with self-heating correction, are demonstrated, using a dual work function gate-first process flow at 100 nm gate pitch and 40 nm fin pitch. Ring-oscillator (RO, FO=3) functionality has been demonstrated, showing excellent Vdd scalability. We have also demonstrated logic scan chain functionality and yield...
The authors explored some of the challenges of the extremely thin SOI technology for mainstream CMOS. Faceted RSD was used to minimize parasitic capacitance. PFET performance is competitive with best bulk CMOS technologies, while NFET performance can be increased by further reduction in the series resistance. The impact of silicon thickness on the device variability was studied to quantify wafer uniformity...
We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced...
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