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Spin-orbit interaction generated spin torque provides a new writing mechanism for spintronics memory devices [1][2][3][4]. This presentation addresses a broad question of how to design spintronics memory devices for match-in-space, content addressable applications utilizing spin-orbit interaction generated spin torque combined with conventional spin torque generated by magnetization polarization....
Traditional spin transfer torque MRAM (STT-MRAM) uses one transistor and one MTJ (1T-1MTJ) architecture, where the transistor provides bi-polar currents to switch the magnetization of the free layer of the MTJ. Due to the limitation of the maximum current that is available from a typical transistor, for a MTJ device with required thermal stability and data retention at extreme densities, the size...
As the CMOS technology scales down, the leakage power becomes a critical barrier for high-performance processors. In addition, the separated processor and storage units in the classic Von-Neumann architecture limit the development of advanced computer design. Spintronics is an emerging platform for nonvolatile memory and logic circuit designs [1-2]. The nonvolatility of spintronics can reduce greatly...
High performance image analytics is an important challenge for big data processing as image and video data is a huge portion of big data e.g. generated by a tremendous amount of image sensors worldwide. This paper presents a case study for image analytics namely the parallel connected component labeling (CCL) which is one of the first steps of image analytics in general. It is shown that a high performance...
Multiprocessor on chip (MPSoC) with network on chip (NoC) are strongly emerging as prime candidates for complex embedded applications. In a general ESL design methodology and for significant size designs the use of prototyping and emulation through FPGA is necessary for intensive validation and test as well as careful design space exploration. Moving a design from FPGA to ASIC questions the gains...
Multiprocessor platforms are gaining markets as a solution to boost general performance of processor beyond technological limitations that are present in single processors chips, Multi-processor in embedded systems also have a future in particular with applications like SDR(Software Defined Radio) where both high performance and high adaptability are required. Cryptographic algorithms implementation...
Embedded system design is increasingly based on single chip multiprocessors because of the high performance and flexibility requirements. Contrary to desktop multi-core and usual multiprocessors, embedded multiprocessors are tightly constrained for the number of external DDR memories due to pin constraints which in turn may affect concurrency access for embedded parallel software implementation. In...
A 1 Mb embedded 2T-SONOS Flash macro is implemented in 0.13 um logic compatible process. The Flash macro has improved reliability and yield with a power-on Successive Approximated Read Calibration (SARC). Word-line decoder area is greatly reduced using 1.8 V transistors to tolerate high voltage. Source degenerated compensation is implemented to enhance read margin. The Flash macro consumes 1.0 mA...
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