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This paper presents bootloader and debugger architectures that are designed for an NoC-based Multiprocessor System On-Chip (MPSoC). An MPSoC demands scalable bootloader and debugger architectures, especially with the increasing of the number of the processor cores. The proposed bootloader and debugger designs utilize the NoC interconnect network to distribute data to and from the cores. With this...
In this paper, we propose a non-weighted load balanced fast local protection scheme for survivable IP networks. Unlike conventional shortest path based routing, we relax shortest path constraints in computing working and backup routes to achieve load balancing purposes. Once a failure occurs, those nodes adjacent to the failure point use their backup routing tables to achieve fast local failure recovery...
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