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FPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. As in many multithreaded applications, communication and synchronization incur significant overheads. Even if these challenges are overcome, the large graph data structures used can quickly...
Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for parameter modifications or do not allow the design to be run at full-speed. Designs are frequently first modeled using a high-level language then later...
Reconfigurable hardware development and debugging tools aspire to provide software-like productivity. A major impediment, however, is the lack of a module linkage capability permitting hardware blocks to be compiled concurrently, limiting the effective use of multi-core and multiprocessor platforms. Although modular and incremental design flows can reuse the layouts of unmodified blocks, non-local...
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