The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Scalability of interface driven perpendicular magnetic anisotropy (i-PMA) magnetic tunnel junctions (MTJs) has been improved down to 1X node which verifies STT-MRAM for future standalone memory. With developing a novel damage-less MTJ patterning process, robust magnetic and electrical performances of i-PMA MTJ cell down to 15 nm node could be achieved.
We investigate the sub-20nm level scalability of STT-MRAM cells possessing perpendicular magnetization induced from the interface of free layer (FL) and MgO tunnel barrier. We demonstrate that the MTJs utilizing dual interfaces of FL and MgO exhibit enhanced scalability with high thermal stability and low switching current, compared with the MTJs with a single interface. As thermal stability factor...
Ultra-high-vacuum (UHV) deposited Ga2O3(Gd2O3) [GGO] has been employed for passivating InGaAs and Ge, without using any interfacial paissivation layers (IPLs). The GGO/InGaAs and /Ge metal-oxide-semiconductor capacitors (MOSCAPs) have exhibited low capacitance-equivalent-thickness (CET) of less than 1nm in GGO, low interfacial densities of states (Dit's) ~ 1011eV-1cm-2, and thermal stability at high...
We have achieved high device performance in self-aligned inversion-channel InGaAs MOSFETs, as well as a CET of <; 1 nm, a Dit ≤ 1011 eV-1cm-2, and high-temperature thermal stability withstanding >850°C RTA in GGO and a CET of <; 1 nm in ALD-HfO2 on InGaAs. Remarkable device performances in self-aligned, inversion-channel Ge MOSFET using GGO without any interfacial passivation layers (IPLs),...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.