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We present a hybrid ARQ (HARQ) scheme using single-error correcting burst-error detecting (SEC-BED) codes to address multiple errors in nanoscale on-chip interconnects. For a given residual flit error rate requirement, the proposed HARQ method yields 20% energy improvement over other burst error correction schemes. By further integrated with skewed transitions, the proposed HARQ method can efficiently...
We present hardware performance analyses of Hamming product codes combined with type-II hybrid automatic repeat request (HARQ), for on-chip interconnects. Input flit width and the number of rows in the product code message are investigated for their impact on the number of wires in the link, codec delay, reliability, and energy consumption. Analytical models are presented to estimate codec delay and...
A multi-wire error correction scheme, which combines Hamming product codes with type-II hybrid ARQ, is proposed for reliable and energy efficient SoC links. Also, a hard decision iterative decoding method, which can achieve the maximum error correction capability of Hamming product codes, is proposed. Simulation results show an improvement of up to four orders of magnitude in residual flit-error rate...
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