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In this paper, we propose a new modeling method for computing coupling capacitance between interconnects on the same or different layers and substrate capacitance in the nanometer very large-scale integration circuits. The model has been developed based on a template, which is obtained on the basis of electric field approximation and followed by a curve-fitting technique to reach promising accuracy...
This paper presents a solution to handling the symmetry and substrate-sharing constraints in the placement design using transitive closure graph (TCG) representation for analog layouts. We propose a new contour-based packing scheme to implement substrate-sharing constraints with the time complexity of O(p· n·lgn), where p is the number of symmetry groups and n is the number of the placed cells. Furthermore,...
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