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As an indispensable portion in the modern system-on-chip designs, analog circuits are becoming more intractable and error prone in the time-consuming design process due to the nature of high parasitic sensitivity along with the shrinking design window in the advanced technology. Compared to the digital counterpart, analog circuits need to be designed more carefully taking into account special analog...
In this paper, we propose a new modeling method for computing coupling capacitance between interconnects on the same or different layers and substrate capacitance in the nanometer very large-scale integration circuits. The model has been developed based on a template, which is obtained on the basis of electric field approximation and followed by a curve-fitting technique to reach promising accuracy...
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