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In this paper a parallel hardware structure of ASIC for HEVC intra prediction encoding is proposed. This structure by analyzing software algorithm, according to the characteristics of the ASIC implementation of parallelization, designs the DC, a planar, horizontal and vertical Angle prediction hardware structure of the parallel processing, and finished the calculation of SATD. A parallel prediction...
HEVC(High Efficiency Video Coding) is a new generation of video coding standard which is proposed by ITU-T VCEG and ISO/IEC MPEG for the increasingly widespread application of high-definition video. On the basis of original DCT transform of H.264, HEVC has proposed a DST transform with the size of 4×4.We design the hardware structure of pipelined DST by analyzing software algorithm, according to the...
Vector quantization (VQ) is widely used in the field of image coding because of its simple decoding algorithm and high compression rate. But owing to its high complexity of image codeword matching process, it is often limited out of some place requisite of real time. In order to accelerate this process, a novel direction classifying criterion is presented in this paper, it is based on the good image...
A high-performance configurable integer motion estimation VLSI architecture based on parallelogram data matching pattern for H.264 is proposed in this paper. Through rational design for the data flow and processing module array, the memory traffic is reduced; data reusability in vertical direction is improved. Furthermore, the number of processing element is configured according to the area-speed...
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