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Potential well engineering is proposed for NAND Flash memory. With a variable (~2nm-4.3nm) tunnel barrier, the engineered well (EW) enhances tunneling of carriers during program/erase (P/E) to result in fast P/E, while it suppresses charge loss under the retention mode to result in good data retention. The EW also improves endurance, as it is insensitive to the P/E stress induced tunnel barrier degradation...
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