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With the technology moving into the deep sub-100-nm region, the increase of leakage power consumption necessitates more aggressive power reduction techniques. Power gating is a promising technique. Our research emphasizes that with the latest and future technologies, power gating operates frequently in its transition mode, especially for aggressive leakage reduction. The dynamic characteristics of...
The continuous increase of leakage power consumption in deep sub-micro technologies necessitates more aggressive leakage control. Runtime leakage control (RTLC) is effective, since runtime circuits generally have significant amount of idleness. However, current RTLC techniques are only used when circuits have long idleness, rendering the techniques less profitable. The reason is due to the large energy...
Run-time Power Gating (RTPG) is a recent technique, which aims at aggressively reducing leakage power consumption. Energy breakeven time (EBT), or equivalent sleep time has been proposed as a critical figure of merit of RTPG. Our research introduces the definition of average EBT in a run-time environment. We develop a method to estimate the average EBT for any given circuit block, considering the...
Run-time active leakage reduction (RALR) is a recent technique and aims at aggressively reducing leakage power consumption. This paper studies the feasibility of RALR from the energy aspect, for both power gating (PG) and reverse body bias (RBB) implementations.We develop two energy saving models for PG and RBB, respectively. These models can accurately estimate the circuit energy saving at any time,...
With the technology moving into the deep sub-100 nm region, the increase of leakage power consumption necessitates more aggressive power reduction techniques. Power gating is a promising technique. Our research emphasizes the virtual ground voltage (VVG) as the key to make critical design trade-offs for power gating. We develop an accurate model to estimate the dynamic VVG value of a circuit block...
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