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To improve via yield and reliability, redundant via insertion is a highly recommended technique proposed by foundries. However, inserting a redundant via can create extra open critical area between nets. A novel redundant via insertion method is proposed in this paper. In this work, we first address the problem of incremental open critical area for redundant via insertion, and then present an open...
With the fast growth of the microelectronic technology, the smaller and smaller feature size of IC (Integrated Circuit) and the increasing circuit complexity, the optimization of layout based on the distribution of defect is becoming more and more important. Firstly, associating critical area with edge network, a concept of shortest path of redundancy material defect is presented and realized. Secondly,...
For modern processes at 90-nm and 65-nm technology nodes, the random yield loss can contribute much to the total yield loss. Hence, it is essential to calculate the critical area to analyze the areas of design, and make changes to improve random yield. The paper provides a novel weighted critical area (WCA) of arbitrary defect outline, which takes the clustering effect in the metal and empty regions...
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