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Nowadays, Graphics Processing Unit (GPU), as a kind of massive parallel processor, has been widely used in general purposed computing tasks. Although there have been mature development tools, it is not a trivial task for programmers to write GPU programs. Based on this consideration, we propose a novel parallel computing architecture. The architecture includes a parallel programming model, named Gemma,...
Volunteer computing has recently received the strong attraction for executing high throughput applications as CPU, storage and network capacities improve and become cheaper. Volunteer resource can provide computing power for cloud computing in many respects, but there is no general survey for appraisal of the suitability of the organization's structure and resources. Therefore, we propose a new comprehensive...
This paper presents a modified pipeline single-path delay feedback (SDF) fast Fourier transform (FFT) architecture. The canonic signed digit (CSD) representation is used to design the function of complex multiplier, which is the main function block in the FFT processor. The processor of a 16-bit 16-point pipeline FFT is realized on the Xilinx Virtex-4 FPGAs. The achieved maximum clock frequency is...
E-commerce (EC) over open devices and networks poses security challenges of a new dimension. This article presents a multi-party contract signing (MPCS) protocol to demonstrate how to apply the secure EC protocols to trading terminals supported by trusted computing (TC) technology. The protocol here reduces the number of rounds to two and the message transmission number to O(n2), which is the best...
The High Level Architecture (HLA) has been followed universally as a de facto standard for modeling and simulation. However, the design of HLA was not intended to manage simulation demanding resources from various organizations. At the same time, the resources of a distributed simulation can not be dynamic mapped during the process. The advantages of Grid service in collaborating and managing distributed...
A new architecture for network on chip (NOC) called Mesh-Tree and its deterministic algorithm has been presented. In this paper, we present an adaptive deadlock-free router. A Mesh-Tree is a multilayered, 3D, pyramidal architecture. Each layer is a mesh and trees are used to connect adjacent layers. This architecture is good for broadcasting and high speed communications. The simulation results show...
This paper presents two novel sorting network-based architectures for computing high sample rate nonrecursive rank order filters. The proposed architectures consist of significantly fewer comparators than existing sorting network-based architectures that are based on bubble-sort and Batcher's odd-even merge sort. The reduction in the number of comparators is obtained by sorting the columns of the...
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