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We present a new 8-transistor (8T) SRAM cell design that uses pMOS devices as cell pass transistors controlled by the write word-line signal. The main advantage of this schema is the composition of a balanced 8T SRAM cell having four nMOS and four pMOS transistor that enables a more compact layout and area reduction. An exhaustive analysis about the impact on key parameters such as leakage consumption,...
Memory design in the nanometer regime imposes specific restrictions to the cell layout structure requiring regular disposition of transistors to minimize the impact of process parameter variations. These layout restrictions invalidate many of the traditional design techniques oriented to improve cell immunity to radiation-induced events that, in turn, get worsened with technology scaling. We analyze...
We analyze two complementary radiation-hardening techniques for 6T SRAM memories compatible with structured layouts. One approach relies on the individual selection of the threshold voltage of each of the four transistors forming the cross-coupled inverters of the SRAM cell. The other one is based on the modification of the widths of all PMOS or all NMOS transistors of the cell. The first technique...
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