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A 6th order Chebyshev active-RC complex filter for high linearity global navigation satellite (GNSS) receiver is proposed in this paper. The filter is synthesized from a 6th order leapfrog low pass filter where the frequency non-ideality compensation technique for integrator is used. High linearity demands a robust and stable IIP3 through the pass band. Meanwhile, the 35dB rejection spec at 1.5 times...
A 12 bit Dual-Rate Hybrid digital-to-analog converter (DAC) architecture with a split Nyquist (1 GS/s) and delta-sigma modulator path (8 GS/s) is proposed and implemented in 65 nm CMOS. Based on the hybrid architecture, the delta-sigma-assisted pre-distortion scheme compensates for the current steering cell mismatch, which further reduces the analog circuit complexity and area. The proposed 8X unrolled...
This paper demonstrated a 5GSample/s track and hold amplifier with 65nm CMOS process. For 6bit ADC application, this work has over 42dBc of SFDR to offer a low distorted signal. The source-degenerated source-couple amplifier with peaking inductance is employed to expand the signal swing and bandwidth, while the power dissipation is maintained as low as possible. The measured power dissipation is 48...
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