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This paper presents an optimized architecture of shared memory controller in packet processing multi-processor system on chip (MPSoC). The rotation priority algorithm in arbitration mechanism is ameliorated so that fairness of the memory access response and continuity of read/write commands are guaranteed. A `ping-pong' structure is adopted in SRAM interface logic which optimizes the memory data throughput...
In this paper an bus architecture combining crossbar switching with split transaction feature is presented for multiprocessor system on chip (MPSoC) in the packet processing application. The high throughput is achieved with crossbar bus topology and low bus latency is finished by split transaction buses which separate address bus from data one. Experimental results show that performance of the proposed...
Consolidated storage service receives its momentum in the building of various IT system infrastructures because of its cost efficiency, reliability, and maintainability. Meanwhile, only when users who run their applications on the consolidated storage system have a similar or better performance experience compared to those using direct-attached storage on each server can the storage design really...
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