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To improve the performance of in-loop deblocking filter in H.264/AVC, this paper proposes a pipelined hardware architecture. A novel transposer design is presented and its hardware cost is reduced by 15% with forwarding logic to shift pixels. Through adopting a filtering order with vertical and horizontal edges processed alternately, on-chip memory is greatly saved and only two 32times32 bits SRAMs...
In this paper, we propose a system-on-chip software hardware co-design for a statistical decoder. We use the context-based adaptive binary arithmetic decoder (CABAC decoder) used in the High profile of the H.264/AVC video coding standard as a design example. The design is aimed to strike a balance between software modules and hardware modules based on design constraints. It is capable of decoding...
Reference Picture Management is complex for hardware implementation. This paper presents an updating strategy for reference picture lists generation by Prime Lists maintenance. Straight insert sorting is used to find out picture insert index. Segmentation and FFA algorithms are applied to quickly adjust frame and field in Initialization stage. Further more, caching technique is used to accelerate...
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