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We fabricated 8Mb 1T-1MTJ STT-MRAM macro embedded in 28nm CMOS logic platform by developing novel integration/stack/patterning technologies. MTJ memory cell array was successfully embedded into Cu backend without open fail and severe degradation of magnetic property. Advanced perpendicular MTJ stack using MgO/CoFeB was developed to show high TMR value of 180% after full integration. In addition, ion...
We have proposed an integrated method to realize MLC PRAM at 45 nm technology node and beyond. It includes reset initialization, Toff skew write, and 2bit write to enhance write-and-verify speed, and 3-cell reference scheme to cope with cell variation due to resistance drift and temperature change. Based on the proposed methods, write throughput can be increased up to SLC level with robust read operation.
We focus here on the promising solutions to overcome thermal-induced erase failure of the unselected neighbor cell while a selected cell is being programmed to reset state with a high-current pulse. Our physical analysis directly demonstrate that this parasitic heating in Ge2Sb2Te5 based cell leads to partial crystallization in the amorphous reset state and to a consequent resistance decrease with...
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