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A 14.4-GS/s 5-b ADC is designed in 40nm CMOS with eight time-interleaved channels of Flash/Successive-Approximation hybrid sub-ADCs each running at 1.6GS/s. A modified bootstrapped track-and-hold switch incorporates a global clock to synchronize the sampling instant of each individual sub-channel, therefore improving multi-phase alignment. Measurement results show that the ADC can achieve a peak SNDR...
A capacitively-divided, injection-locked, ring oscillator is proposed that decreases dynamic power consumption by reducing voltage swing. A feedforward capacitor is placed in series with the load capacitance, effectively AC coupling each inverter stage to the next stage. Simulations are performed using digital programmability of the capacitor weights of both the feedforward and load capacitors, showing...
A single channel, loop-unrolled, asynchronous successive approximation (SAR) ADC fabricated in 40nm CMOS is presented. Compared with a conventional SAR structure that exhibits significant delay in the digital feedback logic, the proposed 6b SAR-ADC employs a different comparator for each bit of conversion, with an asynchronous ripple clock generated after each quantization. With the sample rate limited...
A capacitive charge-sharing, decision feedback equalization (DFE) circuit is presented for use in high-speed serial link receivers. Similar to the capacitive DAC (digital-analog converters) used in successive approximation-based ADCs (analog-digital converters), the proposed one-tap DFE with half-rate quantizer demultipliexing operates at 4Gbps, consuming 0.32 mW from a 1-V supply, excluding clock...
This paper describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency,...
This paper presents a comparative study of clock distribution methods for serial links, including inverter chain, CML chain, transmission line, inductive load and capacitively driven wires in regards to delay, jitter and power consumption. Analysis, simulation and design insights are given for each method for 2.5 GHz clock propagation by on-die 5 mm wire in a 90 nm CMOS process. Simulations show the...
This paper describes a quad-channel, 6.4–8Gbps serial link receiver testchip using a global forwarded clock distribution coupled to local injection-locked ring oscillators in 90nm CMOS. Each receiver consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator for greater than one UI of phase deskew. Measured results show...
This paper presents a theoretical study of a new ladder reflector antenna with standard CMOS process. The antenna consists of an active dipole and a ladder reflector array. The ladder reflector array successfully changes the radiation direction of the active dipole and the ladder reflector antenna radiates majority energy to the outside of the chip. The measured results show that the ladder reflector...
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