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A capacitively-divided, injection-locked, ring oscillator is proposed that decreases dynamic power consumption by reducing voltage swing. A feedforward capacitor is placed in series with the load capacitance, effectively AC coupling each inverter stage to the next stage. Simulations are performed using digital programmability of the capacitor weights of both the feedforward and load capacitors, showing...
This paper describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency,...
This paper describes a quad-channel, 6.4–8Gbps serial link receiver testchip using a global forwarded clock distribution coupled to local injection-locked ring oscillators in 90nm CMOS. Each receiver consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator for greater than one UI of phase deskew. Measured results show...
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