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This paper presents a 5-GS/s 12-way 10-b time-interleaved successive approximation register (SAR) ADC for direct sampling receivers. Proper signal and clock distribution along the multiple channels are utilized to mitigate interchannel bandwidth and timing mismatches. A digitally assisted calibration is introduced to remove the interchannel offset, gain, and timing mismatch. The T-type bootstrapped...
This paper presents a 5GS/s 12-way 10b time-interleaved SAR ADC. Each SAR sub-ADC resolves 11b using reduced radix-2 with 1b redundancy, which tolerates decision errors arising from noise, reference settling error, etc. The top-plate sampling with merged capacitor switching algorithm is applied to achieve high switching efficiency, small area and less comparator noise. Several design techniques for...
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