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The growing complexity of modern digital design makes designers shift toward starting design exploration using high-level languages, and generating register transfer level (RTL) design from system level modeling (SLM) using high-level synthesis or manual transformation. Unfortunately, this translation process is very complex and may introduce bugs into the generated design. In this paper, we propose...
The increasing complexity of digital systems makes designers begin to design using abstract system level modeling (SLM). However, SLM brings new challenges for verification engineers to guarantee the functional equivalence between SLM specifications and lower-level implementations such as those of transaction level modeling (TLM). This paper proposes a novel method for equivalence checking between...
The always increasing complexity of digital system makes designers start the design from more abstract System Level Modeling (SLM). However, the SLM arouses a new challenge for verification engineer to guarantee the functional equivalence between SLM specifications and Transaction Level Modeling (TLM) or other lower level implementations. This paper proposes a novel method for equivalence checking...
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