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In this study, we demonstrate that the performance may be undermined in the state-of-the-art intra-SM sharing schemes for concurrent kernel execution (CKE) on GPUs, due to the interference among concurrent kernels. We highlight that cache partitioning techniques proposed for CPUs are not effective for GPUs. Then we propose to balance memory accesses and limit the number of inflight memory instructions...
Networks on Chip (NoC) has been widely discussed for its smart structure and high performance. Routing algorithms significantly influence design cost and system performance of NoC. In this paper, a new hardware method called Final-Destination-Tag (FDT) is proposed to improve the original Destination-Tag (DT) method for implementing different routing algorithms. Compared with the DT method, the proposed...
Hardware implementation by Networks on Chip (NoC) for Artificial Neural Network (ANN) was proposed to improve. In this work, a new architecture of NoC which has a hardware implementation of routing algorithm is proposed for ANN design. This routing strategy could reduce the packet size of header. The NOXIM NoC simulator is used to simulate the proposed system in term of latency, throughput and power...
Recently, a Network on Chip (NoC) has attracted much attention for its smart structure and high performance. However, NoC routing algorithms significantly influences the performance and design cost. In this paper, a new hardware method to implement a routing algorithm is proposed. The proposed method is used to replace the general destination-tag method for router design. We simulate and evaluate...
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