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Recent processor architectures expose their datapaths to the compiler so that the compiler not only takes care of scheduling instructions to the available processing units but also of scheduling the data transports between the processing units. Bypassing register usage this way generally allows the compiler to improve the degree of instruction-level parallelism. However, the current compiler technology...
Conventional processor architectures are restricted in exploiting instruction level parallelism (ILP) due to the limited number of available registers in their instruction sets. Therefore, recent processor architectures expose their datapaths so that the compiler not only schedules instructions to functional units, but also takes care of directly moving values between functional units avoiding the...
This paper introduces with the selector-tree network a new self-routing and non-blocking interconnection network: The n × n network is capable of routing any permutation of its n inputs to its n output ports and is therefore non-blocking, and thus, more powerful than Ω-permutation and Banyan networks. In contrast to other non-blocking interconnection networks like the Beneš network, our selector-tree...
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