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Shallow trench isolation schemes using a LOCOS edge to avoid sharp corner effects are applied to 0.25 /spl mu/m and 0.18 /spl mu/m technologies. Two variations are studied. In the first case (Case A) a mini-LOCOS is grown and deglazed prior to trench etch whereas in the second case (Case B) the deglaze is omitted. Excellent narrow width effect is demonstrated. The V/sub T/ increases by /spl les/50...
A high performance 1.5 V, sub-0.18 /spl mu/m (physical) gate length CMOS technology and extension to a 1.0 V technology for low power applications is described. nMOS with nominal I/sub drive/=740, 580, and 380 /spl mu/m are achieved for V/sub DD/=1.8, 1.5, and 1.0 V at accumulation t/sub ox/=36 A (from C-V at V/sub gb/=-3 V). pMOS with nominal I/sub drive/ of 300 (1.8 V), 222 (1.5 V), and 140 /spl...
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