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A low-spur PLL is desirable for many applications since it avoides mixing unwanted blocker signals, prevents emission mask violations or minimizes jitter in the clock source. Internal spurs result from the nature of PLL operation and include reference spurs and fractional spurs when the PLL is operated in fractional-N mode. External spurs are caused by nearby disturbances, such as coupling from other...
A dual-rate hybrid DAC is proposed in [1] that shows a path toward high speed/linearity in scaled technology. In this hybrid architecture, the resolution of the DAC is achieved through an oversampled LSB path, while its output power is mostly delivered by a Nyquist MSB path, resulting in a reduced number of current-steering cells and relaxed amplitude-matching requirement via digital pre-distortion...
A 0.6V 10-bit 150MS/s single-channel asynchronous subranging SAR ADC using a settling-time relief technique is presented. The technique extends the allocated DAC settling time with the assistance of a coarse ADC and minimizes digital loop delay so that it can reach high speed and low power at a 0.6V supply. This ADC consumes 0.264mW at 150MS/s in 40nm CMOS technology. It achieves an SNDR of 50.5dB...
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