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This paper describes a general purpose xTCA compliant and FPGA based Data Processing building blocks to be used for trigger and data acquisition system in a big physics experiment with characteristic of high speed data transmission and processing. It features large Field of Programmable Gate Array (FPGA) for data processing, DDR2 memory for data buffering, RocketIO and Gbit Ethernet for data transmission...
An ATCA and FPGA-based Data Processing Unit for PANDA Experiment has been developed. The Unit features 5 Xilinx Virtex-4 FX60 FPGA chips and up to 10 GBytes DDR2 memory. High bandwidth connectivity is provided by 8 additional optical links using RocketIO ports and 5 Gbit Ethernet links to receive data from front-end electronics and transmit the data passed high level trigger to mass storage. A single...
This paper describes the fast control and clock distribution system of BESIII experiment. The function of this system is transmitting fast control signals from trigger system to front-end electronics and readout electronics, receiving status signals from readout electronics for trigger system, and distributing system clock to trigger, front-end and readout electronics. The fast control signals include...
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