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Hot-carrier injection (HCI) at maximum gate current (IG) stress condition for BCD HVPMOS has been studied. It is found that HCI not only causes linear region drain current degradation and minimizes the operation window, but also degrades the gate oxide (GOX) and may result in GOX breakdown. A multistage IDlin degradation behavior has been observed during HCI stress, which is associated with two competing...
Monotonous increase of saturation drain current Idsat but linear-region drain current Idlin reduction during hot carrier injection (HCI) stress is observed in N-type Lateral Diffused MOSFET. But the phenomenon of Idsat increase is contrary to what we typically observed during HCI stress. The increase of Idsat has been attributed to the increase of saturation substrate current Ibsat after HCI stress...
A model predicting the negative bias temperature instability (NBTI) reliability of high performance nitrided oxides is developed from discrete p-type metal-oxide-semiconductor field effect transistor (PMOSFET) data and verified with ring oscillator degradation in various frequencies for up to 1 GHz. Based on the experimental data and the simulation results, hole traps generation is considered to be...
The saturation of a critical gate voltage at 2-2.4 V for SiON with thickness < 1.6 nm (EOT < 1.4 nm) extends the role of digital breakdown (BD) in prolonging progressive BD at nominal voltages. As a result, the post-BD gate leakage degradation rate, which is extrapolated from a high voltage using the conventional approach, is highly overestimated, warranting one to revise the post-BD reliability...
For the first time, a new off-state drain-bias TDDB lifetime model is proposed for DENMOS devices. With the new model, the off-state drain-bias TDDB lifetime can be well predicted from the conventional gate-bias stress without extra long term drain-bias stress. The TDDB lifetime can be decoupled to three components; the small effective stress area and large voltage drop shared by the drain-extension...
A novel ESD device structure with non-LDD at drain region has been demonstrated to enhance the ESD immunity of IO circuits with mixed high/low operation voltage. The protection capability of this novel ESD device structure has been proved from 1 mum to 65 nm technologies with and without fully salicide at the source/drain region. This structure is found to be also very effective to protect the high...
In this work, the "multi-step" power law TDDB model is proposed for ultra thin oxide. The nitrogen concentration effect on the voltage acceleration slope in p-FET is modeled by the boron penetration, and the voltage acceleration slope can be well explained by the "multi-step" power-law TDDB model.
A new Ig-model is proposed to quickly and precisely predict NBTI lifetime for ultra thin oxide (<=3.0nm). The oxide thickness effect on NBTI degradation, recovery and lifetime prediction model are systematically investigated. The mechanism of the NBTI degradation and recovery dependence on oxide thickness is explained as the two-side hydrogen reaction-diffusion mechanism
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