The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents a novel hardening triple-well design for an six-transistors CMOS memory cell fabricated in 65 nm feature size. The new approach calculates the effects of single event transient (SET) with junction currents, which is derived based on device physics. Simulation presents that charge collection can be effectively mitigated with the use of guard ring contact in triple-well CMOS process...
Current characteristics of few-layer BP FETs with 7-nm channel were calculated numerically using Wannier function Hamiltonians with accurate interlayer coupling terms. The potentials in each layer were different for thicker BP devices where large OFF-state current is observed, necessitating a double-gated MOSFET for optimal performance. Elastic acoustic phonon scattering reduced ION by 42%.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.