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We design a single photon avalanche diode (SPAD) in a standard 180-nm CMOS technology. The SPAD consists of a P+/n-well junction with octagon shape, a p-well guard-ring and a ploy guard-ring. The two rings prevent SPAD from premature edge breakdown events and STI interface trap influence, respectively. The measurement results show that a typical dark count rate of SPAD is 8 kHz at room temperature...
A new high density Contact RRAM (CRRAM) cell realized in pure high-k metal gate 28nm CMOS logic process with a very small 35nm×35nm resistive contact hole has been fabricated without extra masking or process step. This study reports the first time of a manufacturable tiny resistive node of RRAM cell on a 28nm CMOS logic platform and fully compatible with high-k metal gate processes. The 28nm Contact...
A 32nm MTP cell with a nitride-based storage node using 32nm strained Si process are demonstrated with an ultra small cell size of 0.0528µm2 by a 32nm strained-CMOS fully logic compatible process. A self-aligned tiny nitride storage node is placed in the narrow spacing of two 32nm transistors by a merged transistor spacer mingled with a strained nitride of 32nm strained Si process. The twin-gate cell...
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