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High density and small size through silicon via is becoming a research and development hotspot of global academia and industry. The density and size of TSV is often constraint with deep reactive ion etching process, TSV filling process and other process as the diameter of TSV decreases to below 20 micrometer or smaller. In this paper, high density and small size TSV array are fabricated (The diameter...
Through silicon via (TSV) technology is moving in the direction of miniaturization and multi-functional development, and is considered to be the main way beyond Moore's Law. This paper presents a fine-pitch TSV manufacturing method with self-aligned backside insulation layer opening for three-dimensional (3D) integration. It is characterized by the use of chemical-mechanical polished (CMP) process...
This paper proposes a combination of annular copper and cylindrical copper as the TSV conductor to decrease the effect of thermal mismatch between copper and silicon in MEMS packaging, which results in a reliability risk between redistribution layer (RDL) and TSV. There are three important factors which may have the most serious influence on the reliability being simulated and analyzed. They are the...
This paper demonstrates a five layers wafer level packaging. This technology has been specially developed for chip scale atomic clock system package. It includes a sealed vapor cell and two supports for vertical-cavity surface-emitting lasers and photodetector. The sealed cavity is achieved by Glass-Silicon-Glass (G-S-G) anodic bonding with high hermeticity, high reliability and low bonding temperature...
In this paper, a novel 3D integration process named Via-Backside-Release process, abbreviated as VBR process, is proposed and technical issues are addressed. With VBR process, there's no need of removal process of copper overburden due to the filling of TSV by copper electroplating, and no individual unit process for producing Cu/Sn microbumps. In order to verify the feasibility of VBR process, a...
Tungsten is a promising bulk material for microsystem applications for its high melting point, radiation resistance, high strength and conductivity. In this paper, wafer level Tungsten-Glass wafer bonding was carried out with photodefinable BCB, the results were compared with Si-Glass bonding. A high-yield BCB bonding technology was developed with good uniformity and relatively high bonding strength,...
TSV interposer provides a cost efficient solution way for 3D IC integration. In this paper, a TSV interposer technology is proposed for SRAM stacking. A simple fabrication process is developed for cost-sensitive application. The mushroomlike Cu/Sn bumps by copper overburden can be directly connected with other substrate, which eliminates a CMP planarization to improve the yield and reduce fabrication...
As multiple layers of planar device are stacked to alleviate signal delay problem and reduce chip area, Through silicon via (TSV) is introduced to replace the large number of long interconnects needed in previous 2D structure. However, the thermal-mechanical reliability problems of TSVs, such as interfacial delamination, via cracking and so on, have become a serious reliability concern. In this paper,...
The fabrication of redistribution layer (RDL) for TSV 3D integration and its optimization are presented in this paper. BCB is selected as the passivation layer and the electroplated Cu is used as the metal layer. CYCLOTENE 3024–46 is utilized and it is deposited by spin-coating and soft cure at 210 °C in annealing oven for 40 minutes with N2 protection. Sputtered Ti/W/Cu and electron beam evaporated...
Sn-Ag-Cu-Mg lead-free solders based on a eutectic Sn-Ag-Cu alloy were prepared by means of orthogonal experimental design. The melting temperature and the wettability of Sn-Ag-Cu-Mg solders were tested by differential thermal analysis (DTA) method and SAT solder checker respectively. Combined with the microstructure analysis, the influence of trace addition of Mg on the melting points and wettability...
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