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Reed–Solomon (RS) codes are widely used in digital communication and storage systems. Algebraic soft-decision decoding (ASD) of RS codes can obtain significant coding gain over the hard-decision decoding (HDD). Compared with other ASD algorithms, the low-complexity Chase (LCC) decoding algorithm needs less computation complexity with similar or higher coding gain. Besides employing complicated interpolation...
An 11.3Gb/s CMOS SONET-compliant transceiver is designed to work in both RZ and NRZ data formats. The TX driver exhibits 17ps rise/fall times, 0.25psrms RJ, and 2pspp DJ. The RX has a multi-stage vertical threshold adjustment circuit. It achieves 5mVpp-diff RX input sensitivity with 0.54UI jitter tolerance. The transceiver core area occupies 1.36mm2 in 65nm CMOS and consumes 214mW.
Clock-gating is a well known technique to reduce dynamic power consumption of a hardware design. In any clock-gating based power reduction flow, automatic selection of appropriate registers and/or register banks is extremely time-consuming because power analysis is performed at the RTL or lower level. In a high-level synthesis (HLS) based design flow, to achieve faster design closure, one must be...
Hardware co-processors are used for accelerating specific compute-intensive tasks dedicated to video/audio codec, encryption/decryption, etc. Since many of these data-processing tasks already have efficient software algorithms, one could reuse those to synthesize the co-processor IPs. However, such software algorithms are usually sequential and written in C/C++. High-level Synthesis (HLS) helps in...
This paper proposes a novel scheme of self-timed charge recycling search-line (SL) drivers for content-addressable memories. In the conventional charge recycling SL driving scheme [11], an additional clock needs to be generated from the system clock with stringent requirements for phase and pulse width to control the charge sharing course. In contrast, the proposed scheme can self-sense the end of...
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