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On-chip interconnect structures become much more complicated and dominate system performance in multi-core SoCs. Oscillation ring test is an efficient test method for most types of faults in the interconnect structures, and previous studies show that a 100% fault coverage and good diagnosis resolution for various fault models is achievable. The test time of oscillation ring test is decided by the...
A synthesis methodology for multiple scan trees that considers output pin limitation, scan chain routing length, test application time and test data compression rate simultaneously is proposed in this paper. Multiple scan trees, also known as a scan forest, greatly reduce test data volume and test application time in SoC testing. However, previous research on scan tree synthesis rarely considered...
This poster presents very-low-voltage (VLV) testing for digital NMOS circuits based on amorphous silicon thin-film (a-Si TFT) transistor technology as an economic alternative to burn-in. A total number of 140 CUT implemented in 8??m a-Si TFT technology are tested at nominal voltage and very-low-voltage. The results indicate that VLV testing is effective in screening out unreliable a-Si TFT circuits.
This paper presents very-low-voltage (VLV) testing for digital NMOS circuits based on amorphous silicon thin film transistor (a-Si TFT) technology. The proposed VLV testing is an economic alternative to burn-in because the former is non-destructive and can be easily performed on regular ATE in a short time. 140 circuits under test (CUT) of two different design styles are implemented in 8 mm a-Si TFT...
Diagnosis for systematic defects is very critical for yield learning in nanometer technology. This paper presents a bridging fault diagnosis which identifies a single layer of systematic defects (LSD), where more than expected numbers of bridging faults are located. The proposed technique is a layout-aware diagnosis which contains bridging pair extraction, structural analysis, and layer-oriented covering...
The degree of achievable test-data compression depends on not only the compression scheme but also the structure of the applied test data. Therefore, it is possible to improve the compression rate of a given test set by carefully organizing the way that test data are present in the scan structure. The relationship between signal probability and test-data entropy is explored in this paper, and the...
This paper presents a response inversion scan cell (RISC) technique to reduce the peak capture power in test mode. The RISC technique inverts the data input of selected scan cells so that peak capture power is reduced. According to the experimental data on ISCAS'89 benchmark circuits, the RISC technique effectively reduces the peak capture power by 45% at a cost of 7.6% area overhead. The presented...
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